Second Generation Delay Model for Submicron CMOS Process

Authors:
M. Rezzoug;Philippe Maurine;Daniel Auvergne
Affiliations:
-;-;-
Venue:
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Year:
2000

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Abstract

The performance characterization and optimization of logic circuits under rapid process migration is one of the big challenges of nowadays submicron CMOS technologies. This characterization must be robust on a wide design space in predicting the performance evolution of designs. In this paper we present a second generation of analytical modeling of delay performance, considering speed carrier desaturation induced non linear variation of delay, I/O coupling, load and input ramp effects. A first model is deduced for inverters and then extended to logic gates through a reduction protocol of the serial transistor array. Validations are given, on a 0.18µm process, by comparing values of simulated (HSPICE) and calculated delay for different configurations of inverters and gates.