Formal sizing rules of CMOS circuits
EURO-DAC '91 Proceedings of the conference on European design automation
A novel macromodel for power estimation in CMOS structures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Based on a concept of equivalent capacitance, previously developed, we present a novel analytical linear representation of internal power dissipation components in CMOS structures. An extension to gates is proposed using an equivalent inverter representation, deduced from the evaluation of an equivalent transistor for serial transistors arrays. Validation of this model is given by comparing the calculated results to the simulated values (using foundries model card), with different design conditions, implemented in 0.25µm and 0.18µm CMOS processes. Application is given to delay and power optimisation of buffer and path.