Internode: Internal Node Logic Computational Model
ANSS '03 Proceedings of the 36th annual symposium on Simulation
UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI
Proceedings of the 2003 international symposium on Low power electronics and design
Application of internode model to global power consumption estimation in SCMOS gates
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A novel macromodel for power estimation in CMOS structures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Power modeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of static CMOS gates: the power dissipated by input transitions that do not produce output switching. In this work, we present an experimental set-up that shows that this power component may contribute up to 59% of the total power consumption of a gate in modern technologies. This fact makes very important to include it into any accurate power model.