Power dissipation reduction during synthesis of two-level logic based on probability of input vectors changes

Authors:
Ireneusz Brzozowski;Andrzej Kos
Affiliations:
AGH University of Science and Technology, Kraków, Poland;AGH University of Science and Technology, Kraków, Poland
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

Citing 3
Cited 1

Logic synthesis for low power VLSI designs

Logic synthesis for low power VLSI designs
Two-level logic minimization for low power

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power reduction and power-delay trade-offs using logic transformations

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

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Abstract

Detailed analysis of CMOS gate behaviour shows that a gate load and input capacitance depends on number of their activated inputs and kind of applied signals i.e. steady state, edge. And in consequence it has an influence on power dissipation. So a reason of the gate switching can be called as the gate driving way. Based on the probability of the gate driving way and associated portion of dissipated energy more accurate model of power dissipation for CMOS gates and circuits is presented. Example of circuits synthesis show power reduction possibilities during design of two-level logic circuits based on information about primary input vector changes – a new circuit activity measure.