Logic synthesis for low power VLSI designs

Logic synthesis for low power

Logic Synthesis and Verification

A new approach to power estimation and reduction in CMOS digital circuits

Integration, the VLSI Journal

Want to save energy?: put intelligence into systems

CSECS'09 Proceedings of the 8th WSEAS International Conference on Circuits, systems, electronics, control & signal processing

Finding the energy efficient curve: gate sizing for minimum power under delay constraints

VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions

Power dissipation reduction during synthesis of two-level logic based on probability of input vectors changes

PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation