Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Logic decomposition during technology mapping
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Processor design for portable systems
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
POSE: power optimization and synthesis environment
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Reducing power dissipation after technology mapping by structural transformations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Inaccuracies in power estimation during logic synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Integrated resynthesis for low power
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Low power design in deep submicron electronics
Low power design in deep submicron electronics
Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Reducing power in high-performance microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computational kernels and their application to sequential power optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Logic synthesis for low power VLSI designs
Logic synthesis for low power VLSI designs
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Common-case computation: a high-level technique for power and performance optimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Kernel-based power optimization of RTL components: exact and approximate extraction algorithms
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Low power synthesis of dual threshold voltage CMOS VLSI circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
The impact of battery capacity and memory bandwidth on CPU speed-setting: a case study
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automating RT-level operand isolation to minimize power consumption in datapaths
DATE '00 Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Low-Power CMOS Design
Dynamic Power Management: Design Techniques and CAD Tools
Dynamic Power Management: Design Techniques and CAD Tools
Power Aware Design Methodologies
Power Aware Design Methodologies
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Design Challenges of Technology Scaling
IEEE Micro
Design for Testability of Gated-Clock FSMs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Power compiler: a gate-level power optimization and synthesis system
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Automatic synthesis of low-power gated-clock finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sequential logic optimization for low power using input-disabling precomputation architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Iterative remapping for logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level power modeling, estimation, and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On determining sensitization criterion in an iterative gate sizing process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On decomposing Boolean functions via extended cofactoring
Proceedings of the Conference on Design, Automation and Test in Europe
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Energy-efficient design of integrated ciecuits requires specialized tools and technologies. This chapter surveys some of the most important contributions in logic synthesis for achieving low-power consumption, by means of gete-level and register-transfer level restructuring. It presents also specialized techniques that leverage specific low-power silicon technologies.