Finite state machine decomposition for low power
DAC '98 Proceedings of the 35th annual Design Automation Conference
Transforming control-flow intensive designs to facilitate power management
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A bipartition-codec architecture to reduce power in pipelined circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
New clock-gating techniques for low-power flip-flops
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Performance analysis of a transaction based software system with shutdown
Proceedings of the 2nd international workshop on Software and performance
Logic Synthesis and Verification
A survey of design techniques for system-level dynamic power management
Readings in hardware/software co-design
Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows
Analog Integrated Circuits and Signal Processing
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
FSM Decomposition for Low Power in FPGA
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A thread partitioning algorithm in low power high-level synthesis
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Power minimization by clock root gating
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Low power synthesis of finite state machines with mixed D and T flip-flops
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Automatic synthesis of clock gating logic with controlled netlist perturbation
Proceedings of the 45th annual Design Automation Conference
A new paradigm for synthesis and propagation of clock gating conditions
Proceedings of the 45th annual Design Automation Conference
Type-matching clock tree for zero skew clock gating
Proceedings of the 45th annual Design Automation Conference
Intelligate: Scalable Dynamic Invariant Learning for Power Reduction
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
A novel sequential circuit optimization with clock gating logic
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Genetic algorithm-based FSM synthesis with area-power trade-offs
Integration, the VLSI Journal
Behavior-level observability don't-cares and application to low-power behavioral synthesis
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Power optimization using dynamic power management
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Improved clock-gating control scheme for transparent pipeline
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Pulser gating: a clock gating of pulsed-latch circuits
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Using SAT-based Craig interpolation to enlarge clock gating functions
Proceedings of the 48th Design Automation Conference
Sub-row sleep transistor insertion for concurrent clock-gating and power-gating
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Active-mode leakage reduction with data-retained power gating
Proceedings of the Conference on Design, Automation and Test in Europe
PowerAdviser: an RTL power platform for interactive sequential optimizations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The automatic synthesis of low power finite-state machines (FSM's) with gated clocks relies on efficient algorithms for synthesis and optimization of dedicated clock-stopping circuitry. We describe a new transformation for incompletely specified Mealy-type machines that makes them suitable for gated-clock implementation with a limited increase in complexity. The transformation is probabilistic-driven, and identifies highly-probable idle conditions that will be exploited for the optimal synthesis of the logic block that controls the local clock of the FSM. We formulate and solve a new logic optimization problem, namely, the synthesis of a subfunction of a Boolean function that is minimal in size under a constraint on its probability to be true. We describe the relevance of this problem for the optimal synthesis of gated clocks. A prototype tool has been implemented and its performance, although influenced by the initial structure of the FSM, shows that sizable power reductions can be obtained using our technique