A case for dynamic pipeline scaling
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Adaptive Pipeline Depth Control for Processor Power-Management
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Pipeline stage unification: a low-energy consumption technique for future mobile processors
Proceedings of the 2003 international symposium on Low power electronics and design
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Improved clock-gating through transparent pipelining
Proceedings of the 2004 international symposium on Low power electronics and design
Automatic synthesis of low-power gated-clock finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A scalable algorithm for RTL insertion of gated clocks based on ODCs computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a stage-level clock-gating scheme for clock power improvement. The proposed technique efficiently implements the concept of transparent pipeline which improves clocking power by dynamically making pipeline registers transparent. We developed new control scheme for transparent pipeline which can be applied to any number of pipeline stages. A low-overhead flip-flop with transparent mode is also proposed to reduce implementation overhead. The proposed clock-gating control logic is extended to pipeline collapsing which allows energy/performance trade-off through dynamic frequency scaling. Simulation results on IBM 90nm technology show that the proposed approach has less overhead (~25%) than the previous transparent pipeline scheme and improves up to 40% of clocking power in 64-bit 7-stage pipeline over traditional stage-level clock-gating technique.