Adaptive Pipeline Structures fo Speculation Control
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Stall cycle redistribution in a transparent fetch pipeline
Proceedings of the 2006 international symposium on Low power electronics and design
ReCycle:: pipeline adaptation to tolerate process variation
Proceedings of the 34th annual international symposium on Computer architecture
Profile-based dynamic pipeline scaling
The Journal of Supercomputing
Reducing branch misprediction penalties via adaptive pipeline scaling
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Compiler support for dynamic pipeline scaling
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
Improved clock-gating control scheme for transparent pipeline
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A CAM with mixed serial-parallel comparison for use in low energy caches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
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A method of managing the power consumption of an embedded, single-issue processor by controlling its pipeline depth is proposed. The execution time will be increased but, if the method is applied to applications with slack time, the user-perceived performance may not be degraded. Two techniques are shown using an existing asynchronous processor as a starting point. The first method controls the pipeline occupancy using a token mechanism, the secondenables adjacent pipeline stages to be merged, by making the latches between them permanently' transparent. An energy reduction of up to 16% is measured, using a collection of five benchmarks.