Reducing TLB power requirements
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Way-predicting set-associative cache for high performance and low energy consumption
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Energy: efficient instruction dispatch buffer design for superscalar processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
An adaptive serial-parallel CAM architecture for low-power cache blocks
Proceedings of the 2002 international symposium on Low power electronics and design
Adaptive Pipeline Depth Control for Processor Power-Management
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Content-addressable memory core cells A survey
Integration, the VLSI Journal
Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A cache-based internet protocol address lookup architecture
Computer Networks: The International Journal of Computer and Telecommunications Networking
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A current-recycling technique for shadow-match-line sensing in content-addressable memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Race-Free Mixed Serial-Parallel Comparison for Low Power Content Addressable Memory
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Low-power high-performance NAND match line content addressable memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of embedded TCAM based longest prefix match search engine
Microprocessors & Microsystems
A multizone pipelined cache for IP routing
NETWORKING'05 Proceedings of the 4th IFIP-TC6 international conference on Networking Technologies, Services, and Protocols; Performance of Computer and Communication Networks; Mobile and Wireless Communication Systems
A low-power ternary content addressable memory with Pai-Sigma matchlines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A novel, low-energy content addressable memory (CAM) structure is presented which achieves an approximately four-fold improvement in energy per access, compared to a standard parallel CAM, when used as tag storage for caches. It exploits the address patterns commonly found in application programs, where testing the four least significant bits of the tag is sufficient to determine over 90% of the tag mismatches; the proposed CAM checks those bits first and evaluates the remainder of the tag only if they match. Although, the energy savings come at the cost of a 25% increase in search time, the proposed CAM organization also supports a parallel operating mode without a speed loss but with reduced energy savings.