Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors
Proceedings of the 2002 international symposium on Low power electronics and design
Cache Memory Design for Internet Processors
IEEE Micro
Routing Table Compaction in Ternary CAM
IEEE Micro
PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
A CAM with mixed serial-parallel comparison for use in low energy caches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
A cache-based internet protocol address lookup architecture
Computer Networks: The International Journal of Computer and Telecommunications Networking
A current-recycling technique for shadow-match-line sensing in content-addressable memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-power TCAM design using mask-aware match-line (MAML) technique
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
A low-power ternary content addressable memory with Pai-Sigma matchlines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A novel low power ripple-precharge Ternary CAM (RPTCAM) architecture is proposed for applications in longest pre- fix matching tasks. The main motivation behind this research is to reduce the dynamic power consumption in TCAM due to frequent charging and discharging of the highly capacitive match line. This issue is addressed by exploiting the fact that when we compare only the first four bits of incoming packet驴s destination address we can identify up to 80% mismatches in the forwarding table. A selective precharge scheme was devised exploiting the above fact wherein the match line is charged only when there is an exact match in the first four bits of TCAM word, thereby significantly reducing the number of transitions in the match line. The parasitics for simulation were extracted from the layout implemented for a 64-32 RP-TCAM architecture using 0