A cache-based internet protocol address lookup architecture

Authors:
Soraya Kasnavi;Paul Berube;Vincent Gaudet;José Nelson Amaral
Affiliations:
Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Alberta, Canada T6G 2V4;Department of Computing Science, University of Alberta, Edmonton, Alberta, Canada T6G 2E8;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Alberta, Canada T6G 2V4;Department of Computing Science, University of Alberta, Edmonton, Alberta, Canada T6G 2E8
Venue:
Computer Networks: The International Journal of Computer and Telecommunications Networking
Year:
2008

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Abstract

This paper proposes a novel Internet Protocol (IP) packet forwarding architecture for IP routers. This architecture is comprised of a non-blocking Multizone Pipelined Cache (MPC) and of a hardware-supported IP routing lookup method. The paper also describes a method for expansion-free software lookups. The MPC achieves lower miss rates than those reported in the literature. The MPC uses a two-stage pipeline for a half-prefix/half-full address IP cache that results in lower activity than conventional caches. MPC's updating technique allows the IP routing lookup mechanism to freely decide when and how to issue update requests. The effective miss penalty of the MPC is reduced by using a small non-blocking buffer. This design caches prefixes but requires significantly less expansion of the routing table than conventional prefix caches. The hardware-based IP lookup mechanism uses a Ternary Content Addressable Memory (TCAM) with a novel Hardware-based Longest Prefix Matching (HLPM) method. HLPM has lower signaling activity in order to process short matching prefixes as compared to alternative designs. HLPM has a simple solution to determine the longest matching prefix and requires a single write for table updates.