ATUM: a new technique for capturing address traces using microcode
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
ARM System Architecture
Routing Table Compaction in Ternary CAM
IEEE Micro
Frequent value encoding for low power data buses
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Ultralow-power SRAM technology
IBM Journal of Research and Development
Content-addressable memory core cells A survey
Integration, the VLSI Journal
A CAM with mixed serial-parallel comparison for use in low energy caches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Scalable IP lookup for Internet routers
IEEE Journal on Selected Areas in Communications
Design of novel CAM core cell structures for an efficient implementation of low power BCAM system
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Low power fast and dense longest prefix match content addressable memory for IP routers
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
A high-speed range-matching TCAM for storage-efficient packet classification
IEEE Transactions on Circuits and Systems Part I: Regular Papers
An error tolerant CAM with nand match-line organization
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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Content addressable memory (CAM) is used in fully associative VLSI lookup circuits for cache memory, translation lookaside buffers (TLBs), and in Internet Protocol (IP) address comparison. In this paper, the use of dynamic NAND match lines is investigated and compared to conventional NOR match lines in cache applications. To achieve high speed, a hierarchical match line is used. The dynamic stack charge-sharing noise immunity, speed, and actual power savings over a conventional NOR match line are investigated using benchmark data. While random patterns are often used when benchmarking CAM match line power, it is shown to be optimistic compared to address trace data, since addresses are highly correlated. It is also shown that proper address input ordering can provide additional power savings. A simple model for the power in dynamic circuit stacks is derived and compared to power simulation data. Additionally, impact on cache tag area and the scaling of the NAND stack to future processes is described.