Detection of SRAM cell stability by lowering array supply voltage
ATS '00 Proceedings of the 9th Asian Test Symposium
Statistical design and optimization of SRAM cell for yield enhancement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistically Aware SRAM Memory Array Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A new single-ended SRAM cell with write-assist
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical design of the 6T SRAM bit cell
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Low-power high-performance NAND match line content addressable memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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An ultralow-standby-power technology has been developed in both 0.18-脗µm and 0.13-脗µm lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage six-transistor (6T) SRAM cell sizes are 4.81 脗µm2 and 2.34 脗µm2, corresponding respectively to the 0.18-脗µm and 0.13-脗µm design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25脗°C and is less than 400 fA per cell at 1.5 V, 85脗°C. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the well-known gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.