Mining association rules between sets of items in large databases
SIGMOD '93 Proceedings of the 1993 ACM SIGMOD international conference on Management of data
An introduction to computational learning theory
An introduction to computational learning theory
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Quickly detecting relevant program invariants
Proceedings of the 22nd international conference on Software engineering
Dynamic Power Management: Design Techniques and CAD Tools
Dynamic Power Management: Design Techniques and CAD Tools
Power Aware Design Methodologies
Power Aware Design Methodologies
A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Data Mining Methods and Models
Data Mining Methods and Models
IODINE: a tool to automatically infer dynamic invariants for hardware designs
Proceedings of the 42nd annual Design Automation Conference
Interactive presentation: PowerQuest: trace driven data mining for power optimization
Proceedings of the conference on Design, automation and test in Europe
A new paradigm for synthesis and propagation of clock gating conditions
Proceedings of the 45th annual Design Automation Conference
Automatic synthesis of low-power gated-clock finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Guarded evaluation: pushing power management to logic synthesis/design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this work we introduce an enhanced methodology to detect dynamic invariants from a power-benchmark simulation trace database. The method is scalable for the application of clock-gating extraction on industrial designs. Our approach focuses upon dynamic simulation data as the main source for detection of opportunities for power reduction. Experimental results demonstrate our ability to learn accurate clock-gating functions from simulation traces and achieve significant power reduction (in the range of 30%-70% of a clock net's power) on industrial micro-processor designs.