Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SYCLOP: Synthesis of CMOS Logic for Low Power Applications
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Automatic synthesis of low-power gated-clock finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power state assignment targeting two- and multilevel logic implementations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integration, the VLSI Journal
Genetic algorithm-based FSM synthesis with area-power trade-offs
Integration, the VLSI Journal
Integration, the VLSI Journal
Low power finite state machine synthesis using power-gating
Integration, the VLSI Journal
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This paper presents a state assignment technique to reduce dynamic power consumption in finite state machines (FSM). The key idea is to decompose the state machine into a set of cycles that are collectively equivalent to the original FSM, and perform state assignment based on the cycle realization of the state machine using Gray codes. A new implementation of state machines by using a combination of D and T flip-flops is thereby proposed, which in conjunction with the proposed encoding algorithm, reduces power consumption by an average of 15%.