Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Activity-driven clock design for low power circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Scheduling techniques to enable power management
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A C-based synthesis system, Bach, and its application (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Novel Formulations for Low-Power Binding of Function Units in High-Level Synthesis
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Automatic synthesis of low-power gated-clock finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a thread partitioning algorithm in low power high-level synthesis. The algorithm is applied to high-level synthesis systems. In the systems, we can describe parallel behaving circuit blocks(threads) explicitly. First it focuses on a local register file RF in a thread. It partitions a thread into two sub-threads, one of which has RF and the other does not have RF. The partitioned sub-threads need to be synchronized with each other to keep the data dependency of the original thread. Since the partitioned sub-threads have waiting time for synchronization, gated clocks can be applied to each sub-thread. Then we can synthesize a low power circuit with a low area overhead, compared to the original circuit. Experimental results demonstrate effectiveness and efficiency of the algorithm.