Communicating sequential processes
Communicating sequential processes
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
DATE '99 Proceedings of the conference on Design, automation and test in Europe
DATE '99 Proceedings of the conference on Design, automation and test in Europe
C-based synthesis experiences with a behavior synthesizer, “cyber”
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A thread partitioning algorithm in low power high-level synthesis
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
An SoC architecture and its design methodology using unifunctional heterogeneous processor array
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Practical Approach for Bus Architecture Optimization at Transaction Level
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
The Challenges of Hardware Synthesis from C-Like Languages
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
The Challenges of Synthesizing Hardware from C-Like Languages
IEEE Design & Test
CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Multi-layer bus minimization for SoC
Journal of Systems and Software
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In system LSI design, a desirable system is one that allows the designer to describe, partition, and verify systems, and to generate circuits efficiently. In this paper, we describe a C-based system LSI design system called Bach which we have developed. Using the example of an MEPG-4 video codec design, we summarize its design flow, effects and current issues.