Communications of the ACM
Integrating program transformations in the memory-based synthesis of image and video algorithms
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Memory estimation for high level synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Efficient context-sensitive pointer analysis for C programs
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
A comprehensive estimation technique for high-level synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
SMASH: a program for scheduling memory-intensive application-specific hardware
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
DATE '99 Proceedings of the conference on Design, automation and test in Europe
C-based synthesis experiences with a behavior synthesizer, “cyber”
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Exact memory size estimation for array computations without loop unrolling
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Towards a new standard for system-level design
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
A C-based synthesis system, Bach, and its application (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Evaluating the effectiveness of pointer alias analyses
Science of Computer Programming - Special issue n static program analysis (SAS'98)
Proceedings of the 14th international symposium on Systems synthesis
Synthesis of hardware models in C with pointers and complex data structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
An integrated algorithm for memory allocation and assignment in high-level synthesis
Proceedings of the 39th annual Design Automation Conference
A comprehensive high-level synthesis system for control-flow intensive behaviors
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Optimizing memory accesses for spatial computation
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Storage requirement estimation for optimized design of data intensive applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Memory access scheduling and binding considering energy minimization in multi-bank memory systems
Proceedings of the 41st annual Design Automation Conference
Automatic translation of software binaries onto FPGAs
Proceedings of the 41st annual Design Automation Conference
Techniques for synthesizing binaries to an advanced register/memory structure
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Memory Accesses Management During High Level Synthesis
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Tartan: evaluating spatial computation for whole program execution
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Efficient hardware code generation for FPGAs
ACM Transactions on Architecture and Code Optimization (TACO)
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Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOMA, a synthesis framework for constructing Memory Access Network (MAN) architectures that inherently enforce memory consistency in the presence of dynamic memory access dependencies. A fundamental bottleneck in any such network is arbitrating between concurrent accesses to a shared memory resource. To alleviate this bottleneck, SOMA uses an application-specific concurrency analysis technique to predict the dynamic memory parallelism profile of the application. This is then used to customize the MAN architecture. Depending on the parallelism profile, the MAN may be optimized for latency, throughput or both. The optimized MAN is automatically synthesized into gate-level structural Verilog using a flexible library of network building blocks. SOMA has been successfully integrated into an automated C-to-hardware synthesis flow, which generates standard cell circuits from unrestricted ANSI-C programs. Post-layout experiments demonstrate that application specific MAN construction significantly improves power and performance.