Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Proceedings of the 43rd annual Design Automation Conference
Tartan: evaluating spatial computation for whole program execution
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method
Proceedings of the conference on Design, automation and test in Europe
NoC design flow for TDMA and QoS management in a GALS context
EURASIP Journal on Embedded Systems
Invited paper: Network-on-Chip design and synthesis outlook
Integration, the VLSI Journal
Developing mesochronous synchronizers to enable 3D NoCs
Proceedings of the conference on Design, automation and test in Europe
Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow
Proceedings of the 2nd international conference on Nano-Networks
Integration, the VLSI Journal
Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
Fundamenta Informaticae - Application of Concurrency to System Design
The aethereal network on chip after ten years: goals, evolution, lessons, and future
Proceedings of the 47th Design Automation Conference
aelite: a flit-synchronous network on chip with composable and predictable services
Proceedings of the Conference on Design, Automation and Test in Europe
The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation
ACM Transactions on Embedded Computing Systems (TECS)
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
Fundamenta Informaticae - Application of Concurrency to System Design
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Guaranteed services (GS) are important in that they provide predictability in the complex dynamics of shared communication structures. This paper discusses the implementation of GS in asynchronous Network-on-Chip. We present a novel scheduling discipline called Asynchronous Latency Guarantee (ALG) scheduling, which provides latency and bandwidth guarantees in accessing a shared media, e.g. a physical link shared between a number of virtual channels. ALG overcomes the drawbacks of existing scheduling disciplines, in particular the coupling between latency and bandwidth guarantees. A 0.12 µm CMOS standard cell implementation of an ALG link has been simulated. The operation speed of the design was 702 MDI/s.