Missing the memory wall: the case for processor/memory integration
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Generalized guaranteed rate scheduling algorithms: a framework
IEEE/ACM Transactions on Networking (TON)
Endpoint admission control: architectural issues and performance
Proceedings of the conference on Applications, Technologies, Architectures, and Protocols for Computer Communication
Asynchronous Macrocell Interconnect using MARBLE
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Guaranteeing the quality of services in networks on chip
Networks on chip
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Operating-system controlled network on chip
Proceedings of the 41st annual Design Automation Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Micro-Network for SoC: Implementation of a 32-Port SPIN network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Cost considerations in network on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Traffic generation and performance evaluation for mesh-based NoCs
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Centralized end-to-end flow control in a best-effort network-on-chip
Proceedings of the 5th ACM international conference on Embedded software
Efficient link capacity and QoS design for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture
ITNG '07 Proceedings of the International Conference on Information Technology
Access Regulation to Hot-Modules in Wormhole NoCs
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Study of NoC Exit Strategies
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A GALS Infrastructure for a Massively Parallel Multiprocessor
IEEE Design & Test
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
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A Token-ManagedAdmission Control (TMAC) mechanism is introduced in order to provide efficient Quality-of-Service (QoS) support for different types of application on a best-effort Globally-Asynchronous Locally-Synchronous (GALS) interconnect fabric. The mechanism is applied at the ingress edges of the fabric using tokens to allocate dynamic network resources and prevent network congestion. The degree of fairness is controllable, in order to balance the desired throughput and data transfer resource allocation appropriately for a particular application. The simulation and analysis presented here shows efficient QoS provision. Our detailed implementation and analysis show that TMAC provides service guarantees on the network while using a modest physical area because of the simplicity of the control logic.