Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip

  • Authors:
  • Xuan-Tu Tran;Jean Durupt;Yvain Thonnart;Francois Bertrand;Vincent Beroulle;Chantal Robach

  • Affiliations:
  • CEA-LETI, France;CEA-LETI, France;CEA-LETI, France;CEA-LETI, France;INPG-LCIS, France;INPG-LCIS, France

  • Venue:
  • NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
  • Year:
  • 2007

Quantified Score

Hi-index 0.00

Visualization

Abstract

The Network-on-Chip (NoC) paradigm has recently emerged as an alternative solution for on-chip communications of the next System-on-Chip (SoC) generation. The advantages of NoC-based systems are numerous: high scalability and versatility, high throughput with good power efficiency,. . . The NoC distributed communication architecture is perfectly adapted to the Globally Asynchronous Locally Synchronous (GALS) platforms where the NoC nodes and links are implemented using asynchronous logic while the computational resources (i.e., IPs) are implemented with standard synchronous design methodologies.