An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator

Authors:
Luis A. Plana;John Bainbridge;Steve Furber;Sean Salisbury;Yebin Shi;Jian Wu
Affiliations:
-;-;-;-;-;-
Venue:
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Year:
2008

Citing 2
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Understanding the interconnection network of SpiNNaker

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A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect

Fundamenta Informaticae - Application of Concurrency to System Design
SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network

Proceedings of the 7th ACM international conference on Computing frontiers
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip

ACM Journal on Emerging Technologies in Computing Systems (JETC)
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect

Fundamenta Informaticae - Application of Concurrency to System Design
Scalable communications for a million-core neural processing architecture

Journal of Parallel and Distributed Computing

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Abstract