Priority Arbiters

Authors:
A. Bystrov;D. J. Kinniment;A. Yakovlev
Affiliations:
-;-;-
Venue:
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Year:
2000

Citing 0
Cited 9

Towards an Efficient Algorithm for Unfolding Petri Nets

CONCUR '01 Proceedings of the 12th International Conference on Concurrency Theory
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Arbiter synthesis approach for SoC multi-processor systems

Computers and Electrical Engineering
QNoC asynchronous router

Integration, the VLSI Journal
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect

Fundamenta Informaticae - Application of Concurrency to System Design
N-way ring and square arbiters

ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Asynchronous spatial division multiplexing router

Microprocessors & Microsystems
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect

Fundamenta Informaticae - Application of Concurrency to System Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Delay-Insensitive specifications model communicating processes that are embedded in a medium that introduces arbitrary and varying delays on the communication channels. In this paper we study transformations of such specifications. The transformations ...