Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Communicating sequential processes
Communications of the ACM
Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems
VLSI-SOC '01 Proceedings of the IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip: SOC Design Methodologies
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
High-Level Asynchronous System Design Using the ACK Framework
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Asynchronous Design Using Commercial HDL Synthesis Tools
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Networks on chip
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
The Future of Formal Methods and GALS Design
Electronic Notes in Theoretical Computer Science (ENTCS)
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This paper presents ASC, an Asynchronous SystemC library, as an extension of SystemC for modeling asynchronous circuits. ASC includes a set of port and channel primitives offering the same communication primitives as the common languages used for asynchronous circuits modeling (CHP, Tangram or Balsa). ASC also offers operators and statements in order to accurately model arbiters, which are the basic components of Asynchronous Network on Chips. The aim of this work is to provide to the designers the means of modeling and verifying asynchronous circuits as well as GALS and NoC systems. Synthesis of ASC models with the help of the TAST framework is under development. As an illustrative example, the modeling of an asynchronous Network-on-Chip architecture using the ASC library is described. This NoC has been successfully integrated into a complex GALS NoC architecture taking advantage of a multi-level SystemC based verification environment.