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Transformations for the synthesis and optimization of asynchronous distributed control
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Logic Synthesis and Verification
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Behavioral synthesis of asynchronous circuits using syntax directed translation as backend
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Delay-Insensitive specifications model communicating processes that are embedded in a medium that introduces arbitrary and varying delays on the communication channels. In this paper we study transformations of such specifications. The transformations ...