System-on-chip beyond the nanometer wall
Proceedings of the 40th annual Design Automation Conference
Transaction level modeling: flows and use models
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
How to bridge the abstraction gap in system level modeling and design
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Communication and configuration controller for NoC based reconfigurable data flow architecture
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
System/network design-space exploration based on TLM for networked embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design
Journal of Signal Processing Systems
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
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Embedded software accounts for more than half of the total development time of a system on a chip (SoC). The complexity of the hardware is becoming so high that the definition of the chip architecture and the verification of the implementation require new techniques. In this chapter we describe our proposed methodology for supporting these new challenges as an extension of the ASIC flow. Our main contribution is the identification and systematic usage in an industrial environment of an abstraction layer that describes SoC architecture to enable three critical activities: early software development, functional verification and architecture analysis. The models are also referred to as Transaction Level Models (TLM) because they rely on the concept of transactions to communicate. Examples of a multimedia platform and of an ARM subsystem highlight practical benefits of our approach.