Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems

• Authors:

• Jean-Baptiste Rigaud;Jerome Quartana;Laurent Fesquet;Marc Renaudin

• Affiliations:

• -;-;-;-

• Venue:
• VLSI-SOC '01 Proceedings of the IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip: SOC Design Methodologies
• Year:
• 2001