Simultaneous scheduling and allocation for cost constrained optimal architectural synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
InSyn: integrated scheduling for DSP applications
DAC '93 Proceedings of the 30th international Design Automation Conference
Comprehensive lower bound estimation from behavioral descriptions
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Computing lower bounds on functional units before scheduling
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
SMASH: a program for scheduling memory-intensive application-specific hardware
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Accurate layout area and delay modeling for system level design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Efficient optimal design space characterization methodologies
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IMPACT: a high-level synthesis system for low power control-flow intensive circuits
Proceedings of the conference on Design, automation and test in Europe
A cycle-accurate compilation algorithm for custom pipelined datapaths
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Compile-time area estimation for LUT-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
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Abstract: We present an integrated approach aimed at predicting layout area needed to implement a behavioral description for a given performance goal. Our approach is novel because: (1) it accounts for all types of RT level components (FUs, buses, registers), (2) it is highly flexible, allowing the designer to tradeoff one type of resource with another and considers dependencies between these different types, (3) it is vertically integrated to include provably accurate physical level estimators, and hence provides realistic accounting of layout effects, and (4) it uses a timing model with finer granularity, accounting for various delays in RTL datapaths. We demonstrate our technique on a variety of HLS benchmarks and show that efficient and effective design space exploration can be accomplished using this technique.