REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Timing analysis in high-level synthesis
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
A comprehensive estimation technique for high-level synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
A reconfigurable arithmetic array for multimedia applications
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
IEEE Transactions on Computers
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators
Journal of VLSI Signal Processing Systems
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
An Overview of the COBRA-ABS High Level Synthesis System for Multi-FPGA Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Accurate Area and Delay Estimators for FPGAs
Proceedings of the conference on Design, automation and test in Europe
How Many CLBs Does Your Circuit Need to be Implemented?
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
The design of dynamically reconfigurable datapath coprocessors
ACM Transactions on Embedded Computing Systems (TECS)
An area estimation methodology for FPGA based designs at systemc-level
Proceedings of the 41st annual Design Automation Conference
Efficient metrics and high-level synthesis for dynamically reconfigurable logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture Exploration for a Reconfigurable Architecture Template
IEEE Design & Test
Computers and Operations Research
Trimaran: an infrastructure for research in instruction-level parallelism
LCPC'04 Proceedings of the 17th international conference on Languages and Compilers for High Performance Computing
Compiler assisted architectural exploration for coarse grained reconfigurable arrays
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
"Smart" design space sampling to predict Pareto-optimal solutions
Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems
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Reconfigurable architecture is one solution to the increasing computational requirement that often cannot be met by the low-end embedded processors. Compiling applications to such architectures involves hardware/software partitioning. To partition the applications, a set of parameters, such as the hardware execution time and hardware area consumption, is required for each application block. Quick derivation of the parameters for all the blocks is essential. Previous research has shown that the coarse-grained reconfigurable architectures are able to accelerate the applications. However, no research effort has been made to find the area and time for application blocks implemented on such architectures. In this paper we present an estimation model for the coarse-grained reconfigurable architectures implemented on FPGA platforms. The estimation model is able to quickly produce an area-time graph, which shows the area and time relationship, for each application block. The accuracy of the estimation model has been verified on real applications. Experiment shows that the estimation error for the area consumption is within 13% and the estimation error for the time is within 8%.