Macro-models for high level area and power estimation on FPGAs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
An area estimation methodology for FPGA based designs at systemc-level
Proceedings of the 41st annual Design Automation Conference
Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations
IEEE Transactions on Computers
High-level synthesis for large bit-width multipliers on FPGAs: a case study
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Fast and accurate resource estimation of automatically generated custom DFT IP cores
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Rapid estimation of control delay from high-level specifications
Proceedings of the 43rd annual Design Automation Conference
Rapid design of area-efficient custom instructions for reconfigurable embedded processing
Journal of Systems Architecture: the EUROMICRO Journal
Area-Time Estimation of Controller for Porting C-Based Functions onto FPGA
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
A framework for core-level modeling and design of reconfigurable computing algorithms
Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Architectural synthesis of fixed-point DSP datapaths using FPGAs
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
Accurate Area, Time and Power Models for FPGA-Based Implementations
Journal of Signal Processing Systems
A complete dynamic power estimation model for data-paths in FPGA DSP designs
Integration, the VLSI Journal
Quipu: A Statistical Model for Predicting Hardware Resources
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Rapid evaluation of custom instruction selection approaches with FPGA estimation
ACM Transactions on Embedded Computing Systems (TECS)
Fast and standalone Design Space Exploration for High-Level Synthesis under resource constraints
Journal of Systems Architecture: the EUROMICRO Journal
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We present an area and delay estimator in the context of a compilerthat takes in high level signal and image processing applicationsdescribed in MATLAB and performs automatic design spaceexploration to synthesize hardware for a Field Programmable GateArray (FPGA) which meets the user area and frequency specifications.We present an area estimator which is used to estimatethe maximum number of Configurable Logic Blocks (CLBs) consumedby the hardware synthesized for the Xilinx XC4010 fromthe input MATLAB algorithm. We also present a delay estimatorwhich finds out the delay in the logic elements in the criticalpath and the delay in the interconnects. The total number of CLBspredicted by us is within 16% of the actual CLB consumption andthe synthesized frequency estimated by us is within an error of13% of the actual frequency after synthesis through Synplify logicsynthesis tools and after placement and routing through the XACTtools from Xilinx. Since the estimators proposed by us are fastand accurate enough, they can be used in a high level synthesisframework like ours to perform rapid design space exploration.