Controller estimation for FPGA target architectures during high-level synthesis
Proceedings of the 15th international symposium on System Synthesis
RTL Synthesis with Physical and Controller Information
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Accurate Area and Delay Estimators for FPGAs
Proceedings of the conference on Design, automation and test in Europe
Rapid estimation of control delay from high-level specifications
Proceedings of the 43rd annual Design Automation Conference
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
Quipu: A Statistical Model for Predicting Hardware Resources
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Rapid area-time estimation is an essential step for efficient design exploration of FPGA-based implementations. In this paper, we focus on area-time estimation of the controller for porting C-based functions onto commercial FPGA devices. We have adopted the one-hot encoding scheme for our FSM model, and devised techniques to estimate area-time of the next-state and control signal decoding logic. Experimental results for the Xilinx Spartan FPGA device show that the proposed model and techniques can lead to reliable area-time estimation. In particular, when compared to results from the commercial tool, the proposed area estimation strategy leads to an average absolute error of only about 10%. In addition, the maximum delay estimation error for the FSM is less than 1ns.