A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Estimating the Complexity of Synthesized Designs from FSM Specifications
IEEE Design & Test
RTL Synthesis with Physical and Controller Information
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Accurate Resource Estimation Algorithms for Behavioral Synthesis
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
How Many CLBs Does Your Circuit Need to be Implemented?
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
An area estimation methodology for FPGA based designs at systemc-level
Proceedings of the 41st annual Design Automation Conference
High-level synthesis for large bit-width multipliers on FPGAs: a case study
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Rapid estimation of control delay from high-level specifications
Proceedings of the 43rd annual Design Automation Conference
Area-Time Estimation of Controller for Porting C-Based Functions onto FPGA
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
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In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence, especially, if a certain data-path realization requires a huge number of states and/or con trol signals. This paper presents a new approach on controller estimation during high-level synthesis for FPGA-based target architectures. The estimator, presented in this paper can be invoked after or during every synthesis-step, i.e. allocation, scheduling and binding, respectively. By considering the control ler influence on the overall area of a design, design space explo ration can be made more accurate and less error prone. We present an approach for estimating area of the controller based on information which are easily accessible during each step of high-level synthesis, so no explicit description of the controller, which usually will be generated after the binding, is necessary. This is particularly valuable in the allocation phase, where intensive design space explorations have to be done, based on fast and accurate estimates.