Controller estimation for FPGA target architectures during high-level synthesis
Proceedings of the 15th international symposium on System Synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compiling Scilab to high performance embedded multicore systems
Microprocessors & Microsystems
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Given a scheduled data ow graph the functional, storage, and interconnect (multiplexors) resources are analytically estimated taking into account the effects of post-scheduling tasks. Complexity of the controller implementation is also estimated. The novelty of this work lies in predicting the effects of the post-scheduling tasks on the final amount of resources, the effects of data path resource optimization on the controller complexity. Experimental results show high correlation between estimated and actual numbers.