Multiplication by Integer constants
Software—Practice & Experience
Journal of Computational Physics
ACM SIGPLAN Notices
Journal of Parallel and Distributed Computing
Hacker's Delight
Architecture Exploration for Embedded Processors with Lisa
Architecture Exploration for Embedded Processors with Lisa
Simple Generation of Static Single-Assignment Form
CC '00 Proceedings of the 9th International Conference on Compiler Construction
FPGA resource and timing estimation from Matlab execution traces
Proceedings of the tenth international symposium on Hardware/software codesign
Accurate Resource Estimation Algorithms for Behavioral Synthesis
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Distinctive Image Features from Scale-Invariant Keypoints
International Journal of Computer Vision
Evaluation of SIMD Architecture Enhancement in Embedded Processors for MPEG-4
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Mapping Applications to Tiled Multiprocessor Embedded Systems
ACSD '07 Proceedings of the Seventh International Conference on Application of Concurrency to System Design
Floating-to-fixed-point conversion for digital signal processors
EURASIP Journal on Applied Signal Processing
Towards software defined radios using coarse-grained reconfigurable hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2009 ACM SIGPLAN conference on Programming language design and implementation
Polyhedral-Model Guided Loop-Nest Auto-Vectorization
PACT '09 Proceedings of the 2009 18th International Conference on Parallel Architectures and Compilation Techniques
Examination timetabling using late acceptance hyper-heuristics
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
KAHRISMA: a novel hypermorphic reconfigurable-instruction-set multi-grained-array architecture
Proceedings of the Conference on Design, Automation and Test in Europe
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Data layout transformation for stencil computations on short-vector SIMD architectures
CC'11/ETAPS'11 Proceedings of the 20th international conference on Compiler construction: part of the joint European conferences on theory and practice of software
IPDPSW '11 Proceedings of the 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum
Reconfigurable Computing: From FPGAs to Hardware/Software Codesign
Reconfigurable Computing: From FPGAs to Hardware/Software Codesign
Computer Generation of Hardware for Linear Digital Signal Processing Transforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Compiler Back-End for Reconfigurable, Mixed-ISA Processors with Clustered Register Files
IPDPSW '12 Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum
A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The mapping process of high performance embedded applications to today's multiprocessor system-on-chip devices suffers from a complex toolchain and programming process. The problem is the expression of parallelism with a pure imperative programming language, which is commonly C. This traditional approach limits the mapping, partitioning and the generation of optimized parallel code, and consequently the achievable performance and power consumption of applications from different domains. The Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of a Scilab-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from a high level of abstraction. The holistic solution of the ALMA toolchain allows the complexity of both the application and the architecture to be hidden, which leads to better acceptance, reduced development cost, and shorter time-to-market. Driven by the technology restrictions in chip design, the end of exponential growth of clock speeds and an unavoidable increasing request of computing performance, ALMA is a fundamental step forward in the necessary introduction of novel computing paradigms and methodologies.