Data layout transformation for stencil computations on short-vector SIMD architectures

  • Authors:

  • Tom Henretty;Kevin Stock;Louis-Noël Pouchet;Franz Franchetti;J. Ramanujam;P. Sadayappan

  • Affiliations:

  • The Ohio State University;The Ohio State University;The Ohio State University;Carnegie Mellon University;Louisiana State University;The Ohio State University

  • Venue:
  • CC'11/ETAPS'11 Proceedings of the 20th international conference on Compiler construction: part of the joint European conferences on theory and practice of software
  • Year:
  • 2011

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Abstract

Stencil computations are at the core of applications in many domains such as computational electromagnetics, image processing, and partial differential equation solvers used in a variety of scientific and engineering applications. Short-vector SIMD instruction sets such as SSE and VMX provide a promising and widely available avenue for enhancing performance on modern processors. However a fundamental memory stream alignment issue limits achieved performance with stencil computations on modern short SIMD architectures. In this paper, we propose a novel data layout transformation that avoids the stream alignment conflict, along with a static analysis technique for determining where this transformation is applicable. Significant performance increases are demonstrated for a variety of stencil codes on three modern SIMD-capable processors.