MAPS: an integrated framework for MPSoC application parallelization
Proceedings of the 45th annual Design Automation Conference
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Generation and calibration of compositional performance analysis models for multi-processor systems
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Combining mapping and partitioning exploration for NoC-based embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms
Journal of Systems Architecture: the EUROMICRO Journal
Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms
Proceedings of the Conference on Design, Automation and Test in Europe
Improving platform-based system synthesis by satisfiability modulo theories solving
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Modeling and analyzing real-time multiprocessor systems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
MPSoC programming using the MAPS compiler
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Verification of printer datapaths using timed automata
ISoLA'10 Proceedings of the 4th international conference on Leveraging applications of formal methods, verification, and validation - Volume Part II
D-finder 2: towards efficient correctness of incremental design
NFM'11 Proceedings of the Third international conference on NASA Formal methods
Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessors
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Thermal-aware system analysis and software synthesis for embedded multi-processors
Proceedings of the 48th Design Automation Conference
A formal approach for incremental construction with an application to autonomous robotic systems
SC'11 Proceedings of the 10th international conference on Software composition
Mapping of applications to MPSoCs
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Analysis and optimization of fault-tolerant task scheduling on multiprocessor embedded systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A middleware approach to achieving fault tolerance of Kahn process networks on networks on chips
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
PRO3D: programming for future 3D manycore architectures
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
ACM Transactions on Embedded Computing Systems (TECS)
Rigorous system design: the BIP approach
MEMICS'11 Proceedings of the 7th international conference on Mathematical and Engineering Methods in Computer Science
Towards fault-tolerant embedded systems with imperfect fault detection
Proceedings of the 49th Annual Design Automation Conference
Communication-aware mapping of KPN applications onto heterogeneous MPSoCs
Proceedings of the 49th Annual Design Automation Conference
MpAssign: A Framework for Solving the Many-Core Platform Mapping Problem
Software—Practice & Experience
Integrating Memory Optimization with Mapping Algorithms for Multi-Processors System-on-Chip
ACM Transactions on Embedded Computing Systems (TECS)
Scenario-based design flow for mapping streaming applications onto on-chip many-core systems
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Mapping of streaming applications considering alternative application specifications
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Predictability for timing and temperature in multiprocessor system-on-chip platforms
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
A rule-based quasi-static scheduling approach for static islands in dynamic dataflow graphs
ACM Transactions on Embedded Computing Systems (TECS)
A compiler infrastructure for embedded heterogeneous MPSoCs
Proceedings of the 2013 International Workshop on Programming Models and Applications for Multicores and Manycores
Mapping on multi/many-core systems: survey of current and emerging trends
Proceedings of the 50th Annual Design Automation Conference
Multi-objective aware extraction of task-level parallelism using genetic algorithms
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A system-level infrastructure for multidimensional MP-SoC design space co-exploration
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
Expandable process networks to efficiently specify and explore task, data, and pipeline parallelism
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
Compiling Scilab to high performance embedded multicore systems
Microprocessors & Microsystems
ASP-based optimized mapping in a simulink-to-MPSoC design flow
Journal of Systems Architecture: the EUROMICRO Journal
Microprocessors & Microsystems
A compiler infrastructure for embedded heterogeneous MPSoCs
Parallel Computing
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Modern multiprocessor embedded systems execute a large number of tasks on shared processors and handle their complex communications on shared communication networks. Traditional methods from the HW/SW codesign or general purpose computing domain cannot be applied any more to cope with this new class of complex systems. To overcome this problem, a framework called Distributed Operation Layer (DOL) is proposed that enables the efficient execution of parallel applications on multiprocessor platforms. Two main services are offered by the DOL: systemlevel performance analysis and multi-objective algorithmarchitecture mapping. This paper presents the basic principles of the DOL, the specification mechanisms for applications, platform and mapping as well as its internal analytic performance evaluation framework. To illustrate the presented concepts, an MPEG-2 decoder case study is presented.