MAST: Modeling and Analysis Suite for Real Time Applications
ECRTS '01 Proceedings of the 13th Euromicro Conference on Real-Time Systems
A General Framework for Analysing System Properties in Platform-Based Embedded System Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design Space Exploration and System Optimization with SymTA/S " Symbolic Timing Analysis for Systems
RTSS '04 Proceedings of the 25th IEEE International Real-Time Systems Symposium
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Throughput Analysis of Synchronous Data Flow Graphs
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
QEST '06 Proceedings of the 3rd international conference on the Quantitative Evaluation of Systems
Coloured Petri Nets and CPN Tools for modelling and validation of concurrent systems
International Journal on Software Tools for Technology Transfer (STTT)
Mapping Applications to Tiled Multiprocessor Embedded Systems
ACSD '07 Proceedings of the Seventh International Conference on Application of Concurrency to System Design
Formal Modeling and Scheduling of Datapaths of Digital Document Printers
FORMATS '08 Proceedings of the 6th international conference on Formal Modeling and Analysis of Timed Systems
Roofline: an insightful visual performance model for multicore architectures
Communications of the ACM - A Direct Path to Dependable Software
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
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In multiprocessor systems with many data-intensive tasks, a bus may be among the most critical resources. Typically, allocation of bandwidth to one (high-priority) task may lead to a reduction of the bandwidth of other tasks, and thereby effectively slow down these tasks. WCET analysis for these types of systems is a major research challenge. In this paper, we show how the dynamic behavior of a memory bus and a USB in a realistic printer application can be faithfully modeled using timed automata. We analyze, using Uppaal, the worst case latency of scan jobs with uncertain arrival times in a setting where the printer is concurrently processing an infinite stream of print jobs.