A machine program for theorem-proving
Communications of the ACM
System-level synthesis of adaptive computing systems
System-level synthesis of adaptive computing systems
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
System architecture evaluation using modular performance analysis: a case study
International Journal on Software Tools for Technology Transfer (STTT)
Mapping Applications to Tiled Multiprocessor Embedded Systems
ACSD '07 Proceedings of the Seventh International Conference on Application of Concurrency to System Design
Performance analysis of FlexRay-based ECU networks
Proceedings of the 44th annual Design Automation Conference
Efficient symbolic multi-objective design space exploration
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A retargetable parallel-programming framework for MPSoC
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Daedalus: toward composable multimedia MP-SoC design
Proceedings of the 45th annual Design Automation Conference
System-on-chip environment: a SpecC-based framework for heterogeneous MPSoC design
EURASIP Journal on Embedded Systems - C-Based Design of Heterogeneous Embedded Systems
Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis
Proceedings of the 46th Annual Design Automation Conference
A structure-based variable ordering heuristic for SAT
IJCAI'03 Proceedings of the 18th international joint conference on Artificial intelligence
A fast linear-arithmetic solver for DPLL(T)
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
DPLL(T) with exhaustive theory propagation and its application to difference logic
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Symbolic system synthesis in the presence of stringent real-time constraints
Proceedings of the 48th Design Automation Conference
Concurrent architecture and schedule optimization of time-triggered automotive systems
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A satisfiability approach to speed assignment for distributed real-time systems
Proceedings of the Conference on Design, Automation and Test in Europe
Priority assignment for event-triggered systems using mathematical programming
Proceedings of the Conference on Design, Automation and Test in Europe
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Optimizing the implementation of real-time Simulink models onto distributed automotive architectures
Journal of Systems Architecture: the EUROMICRO Journal
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Due to the ever increasing system complexity, deciding whether a given platform is sufficient to implement a set of applications under given constraints becomes a serious bottleneck in platform-based design. As a remedy, the work at hand proposes a novel automatic platform-based system synthesis procedure, inspired by techniques developed in the context of automatic system verification known as Satisfiability Modulo Theories. It tightly couples the computation of a feasible allocation and binding with nonfunctional constraint checking where, in contrast to existing approaches, not only linear constraints but even nonlinear constraints are supported. This allows to efficiently prove whether there exists a feasible implementation of a set of applications on the given platform with respect to both, functional and nonfunctional constraints. Moreover, an approach for early learning based on feasibility checking of partial implementations is proposed that can significantly improve the synthesis runtime, especially in case the selected platform imposes stringent constraints on the implementation. The effectiveness of this approach is shown for an automotive ECU network design that requires Modular Performance Analysis to ensure nonfunctional nonlinear timing constraints.