Specification and design of embedded systems
Specification and design of embedded systems
CoWare—a design environment for heterogenous hardware/software systems
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
A programming environment for the design of complex high speed ASICs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Multilanguage design of heterogeneous systems
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Hardware/software partitioning of embedded system in OCAPI-xl
Proceedings of the ninth international symposium on Hardware/software codesign
Proceedings of the 38th annual Design Automation Conference
System Design with SystemC
Optimal message-passing for data coherency in distributed architecture
Proceedings of the 15th international symposium on System Synthesis
Multiprocessor SoC Platforms: A Component-Based Design Approach
IEEE Design & Test
Retargetable profiling for rapid, early system-level design space exploration
Proceedings of the 41st annual Design Automation Conference
Embedded software generation from system level design languages
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
RTOS Modeling for System Level Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Verification of system level model transformations
International Journal of Parallel Programming
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
SystemC-based modelling, seamless refinement, and synthesis of a JPEG 2000 decoder
Proceedings of the conference on Design, automation and test in Europe
An interactive design environment for C-based high-level synthesis of RTL processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic Layer-Based Generation of System-On-Chip Bus Communication Models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Specify-explore-refine (SER): from specification to implementation
Proceedings of the 45th annual Design Automation Conference
Fast and accurate processor models for efficient MPSoC design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Electronic system-level synthesis methodologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improving platform-based system synthesis by satisfiability modulo theories solving
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Platform modeling for exploration and synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
System-level development of embedded software
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Multi-core parallel simulation of system-level description languages
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Symbolic system synthesis in the presence of stringent real-time constraints
Proceedings of the 48th Design Automation Conference
A Model-Driven Design Framework for Massively Parallel Embedded Systems
ACM Transactions on Embedded Computing Systems (TECS)
Computer-Aided Recoding to Create Structured and Analyzable System Models
ACM Transactions on Embedded Computing Systems (TECS)
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Task-level data model for hardware synthesis based on concurrent collections
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Efficient traffic aware power management in multicore communications processors
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
Out-of-order parallel simulation for ESL design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Solving system-level synthesis problem by a multi-objective estimation of distribution algorithm
Expert Systems with Applications: An International Journal
ASP-based optimized mapping in a simulink-to-MPSoC design flow
Journal of Systems Architecture: the EUROMICRO Journal
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The constantly growing complexity of embedded systems is a challenge that drives the development of novel design automation techniques. C-based system-level design addresses the complexity challenge by raising the level of abstraction and integrating the design processes for the heterogeneous system components. In this article, we present a comprehensive design framework, the system-on-chip environment (SCE) which is based on the influential SpecC language and methodology. SCE implements a top-down system design flow based on a specify-explore-refine paradigm with support for heterogeneous target platforms consisting of custom hardware components, embedded software processors, dedicated IP blocks, and complex communication bus architectures. Starting from an abstract specification of the desired system, models at various levels of abstraction are automatically generated through successive step-wise refinement, resulting in a pin-and cycle-accurate system implementation. The seamless integration of automatic model generation, estimation, and verification tools enables rapid design space exploration and efficient MPSoC implementation. Using a large set of industrial-strength examples with a wide range of target architectures, our experimental results demonstrate the effectiveness of our framework and show significant productivity gains in design time.