Efficient flow-sensitive interprocedural computation of pointer-induced aliases and side effects
POPL '93 Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Undecidability of static analysis
ACM Letters on Programming Languages and Systems (LOPLAS)
Specification and design of embedded systems
Specification and design of embedded systems
The undecidability of aliasing
ACM Transactions on Programming Languages and Systems (TOPLAS)
Efficient context-sensitive pointer analysis for C programs
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Points-to analysis in almost linear time
POPL '96 Proceedings of the 23rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Program decomposition for pointer aliasing: a step toward practical analyses
SIGSOFT '96 Proceedings of the 4th ACM SIGSOFT symposium on Foundations of software engineering
Connection analysis: a practical interprocedural heap analysis for C
International Journal of Parallel Programming - Special issue: selected papers from the eighth international workshop on languages and compilers for parallel computing
Transformational partitioning for co-design of multiprocessor systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Scalable context-sensitive flow analysis using instantiation constraints
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Pointer analysis: haven't we solved this problem yet?
PASTE '01 Proceedings of the 2001 ACM SIGPLAN-SIGSOFT workshop on Program analysis for software tools and engineering
Multiprocessor SoC Platforms: A Component-Based Design Approach
IEEE Design & Test
Array recovery and high-level transformations for DSP applications
ACM Transactions on Embedded Computing Systems (TECS)
Array Data Dependence Testing with the Chains of Recurrences Algebra
IWIA '04 Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Pointer Analysis for Source-to-Source Transformations
SCAM '05 Proceedings of the Fifth IEEE International Workshop on Source Code Analysis and Manipulation
An empirical evaluation of chains of recurrences for array dependence testing
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
SPRINT: a tool to generate concurrent transaction-level models from sequential code
EURASIP Journal on Applied Signal Processing
Pointer re-coding for creating definitive MPSoC models
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Creating Explicit Communication in SoC Models Using Interactive Re-Coding
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Automatic re-coding of reference code into structured and analyzable SoC models
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models
Proceedings of the 45th annual Design Automation Conference
Specify-explore-refine (SER): from specification to implementation
Proceedings of the 45th annual Design Automation Conference
System-on-chip environment: a SpecC-based framework for heterogeneous MPSoC design
EURASIP Journal on Embedded Systems - C-Based Design of Heterogeneous Embedded Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Designer-in-the-loop recoding of ESL models using static parallel access conflict analysis
Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems
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In embedded system design, the quality of the input model has a direct bearing on the effectiveness of the system exploration and synthesis tools. Given a well-written system model, tools today are effective in generating working implementations. However, readily available C reference code is not conducive for immediate system synthesis as it lacks needed features for automatic analysis and synthesis. Among others, the lack of proper structure and the presence of intractable pointers in the reference code are factors that seriously hamper the effectiveness of system design tools. To overcome these deficiencies, we aim to automate the conversion of flat C code into a well-structured system model by applying automated source code transformations. We present a set of computer-aided recoding operations that enable the system designer to mitigate pointer problems and quickly create the necessary structural hierarchy so that the design model becomes easily analyzable and synthesizable. Utilizing the designer’s knowledge, our interactive recoding transformations aid the designer in efficiently creating well-structured system models for rapid design space exploration and successful synthesis. Our estimated and measured experimental results show significant productivity gains through a substantial reduction of the model creation time.