Advanced compiler optimizations for supercomputers
Communications of the ACM - Special issue on parallelism
Communications of the ACM
An HPF compiler for the IBM SP2
Supercomputing '95 Proceedings of the 1995 ACM/IEEE conference on Supercomputing
A programmer's guide to ZPL
Program Improvement by Source-to-Source Transformation
Journal of the ACM (JACM)
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
Advances in the dataflow computational model
Parallel Computing - Special Anniversary issue
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Embedded Multiprocessors: Scheduling and Synchronization
Embedded Multiprocessors: Scheduling and Synchronization
A Loop Transformation Theory and an Algorithm to Maximize Parallelism
IEEE Transactions on Parallel and Distributed Systems
Power Evaluation of a Handheld Computer
IEEE Micro
Pipelining Wavefront Computations: Experiences and Performance
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Interactive Compilation and Performance Analysis with URSA MINOR
LCPC '97 Proceedings of the 10th International Workshop on Languages and Compilers for Parallel Computing
FP-Map - An Approach to the Functional Pipelining of Embedded Programs
HIPC '97 Proceedings of the Fourth International Conference on High-Performance Computing
Translating affine nested-loop programs to process networks
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Decoupled Software Pipelining with the Synchronization Array
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
From Sequential Programs to Concurrent Threads
IEEE Computer Architecture Letters
Compiling for stream processing
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
A fast technique for identifying zerotrees in the EZW algorithm
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 03
Memory centric design of an MPEG-4 video encoder
IEEE Transactions on Circuits and Systems for Video Technology
Design and Tool Flow of Multimedia MPSoC Platforms
Journal of Signal Processing Systems
Software metadata: Systematic characterization of the memory behaviour of dynamic applications
Journal of Systems and Software
Iterative probabilistic performance prediction for multi-application multiprocessor systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Safari Through the MPSoC Run-Time Management Jungle
Journal of Signal Processing Systems
A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms
Proceedings of the 47th Design Automation Conference
Exploring parallelizations of applications for MPSoC platforms using MPA
Proceedings of the Conference on Design, Automation and Test in Europe
Computer-Aided Recoding to Create Structured and Analyzable System Models
ACM Transactions on Embedded Computing Systems (TECS)
Designer-in-the-loop recoding of ESL models using static parallel access conflict analysis
Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems
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A high-level concurrent model such as a SystemC transaction-level model can provide early feedback during the exploration of implementation alternatives for state-of-the-art signal processing applications like video codecs on a multiprocessor platform. However, the creation of such a model starting from sequential code is a time-consuming and error-prone task. It is typically done only once, if at all, for a given design. This lack of exploration of the design space often leads to a suboptimal implementation. To support our systematic C-based design flow, we have developed a tool to generate a concurrent SystemC transaction-level model for user-selected task boundaries. Using this tool, different parallelization alternatives have been evaluated during the design of an MPEG-4 simple profile encoder and an embedded zero-tree coder. Generation plus evaluation of an alternative was possible in less than six minutes. This is fast enough to allow extensive exploration of the design space.