Designer-in-the-loop recoding of ESL models using static parallel access conflict analysis

Authors:
Xu Han;Weiwei Chen;Rainer Dömer
Affiliations:
University of California, Irvine;University of California, Irvine;University of California, Irvine
Venue:
Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems
Year:
2013

Citing 9
Cited 0

System Design: A Practical Guide with Specc

System Design: A Practical Guide with Specc
Maximizing Multiprocessor Performance with the SUIF Compiler

Computer
Multiprocessor SoC Platforms: A Component-Based Design Approach

IEEE Design & Test
SPRINT: a tool to generate concurrent transaction-level models from sequential code

EURASIP Journal on Applied Signal Processing
Predictive runtime verification of multi-processor SoCs in SystemC

Proceedings of the 45th annual Design Automation Conference
Race analysis for systemc using model checking

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming

CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Computer-Aided Recoding to Create Structured and Analyzable System Models

ACM Transactions on Embedded Computing Systems (TECS)
Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

At the Electronic System Level (ESL), a well-defined design model enables early design space exploration and automatic synthesis on custom multiprocessor platforms. However, the initial design model is usually manually recoded from unstructured and sequential source code. To efficiently create cleanly structured and parallel models, this paper proposes a designer-in-the-loop approach on Eclipse platform where the system model is analyzed and recoded using automated functions. Particularly, advanced static analysis at compile time can guarantee that the parallelism in the model is safe and free from race conditions. Experiments using the tool with a class of graduate students show significant productivity gains and error reduction in model creation.