Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Relative scheduling under timing constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Redundant operator creation: a scheduling optimization technique
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Critical path minimization using retiming and algebraic speed-up
DAC '93 Proceedings of the 30th international Design Automation Conference
Compiler transformations for high-performance computing
ACM Computing Surveys (CSUR)
Global scheduling with code-motions for high-level synthesis applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new framework for exhaustive and incremental data flow analysis using DJ graphs
PLDI '96 Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation
Incremental computation of dominator trees
ACM Transactions on Programming Languages and Systems (TOPLAS)
A specification invariant technique for operation cost minimisation in flow-graphs
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Decomposition of timed decision tables and its use in presynthesis optimizations
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Advanced compiler design and implementation
Advanced compiler design and implementation
High-level address optimization and synthesis techniques for data-transfer-intensive applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
C-based synthesis experiences with a behavior synthesizer, “cyber”
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Behavioral network graph: unifying the domains of high-level and logic synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A global resource-constrained parallelization technique
ICS '89 Proceedings of the 3rd international conference on Supercomputing
Partial redundancy elimination in SSA form
ACM Transactions on Programming Languages and Systems (TOPLAS)
Analysis of high-level address code transformations for programmable processors
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Speculation techniques for high level synthesis of control intensive designs
Proceedings of the 38th annual Design Automation Conference
Conditional speculation and its effects on performance and area for high-level snthesis
Proceedings of the 14th international symposium on Systems synthesis
Coordinated transformations for high-level synthesis of high performance microprocessor blocks
Proceedings of the 39th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
High-Level VLSI Synthesis
Dynamic common sub-expression elimination during scheduling in high-level synthesis
Proceedings of the 15th international symposium on System Synthesis
Symbolic algebra and timing driven data-flow synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Automatic Extraction of Functional Parallelism from Ordinary Programs
IEEE Transactions on Parallel and Distributed Systems
Mutation Scheduling: A Unified Approach to Compiling for Fine-Grain Parallelism
LCPC '94 Proceedings of the 7th International Workshop on Languages and Compilers for Parallel Computing
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
An Efficient Global Resource-Directed Approach to Exploiting Instruction-Level Parallelism
PACT '96 Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques
Automata-based symbolic scheduling
Automata-based symbolic scheduling
A new symbolic technique for control-dependent scheduling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new algorithm for elimination of common subexpressions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wavesched: a novel scheduling technique for control-flow intensive designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance-driven high-level synthesis with bit-level chaining and clock selection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using global code motions to improve the quality of results for high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
The impact of loop unrolling on controller delay in high level synthesis
Proceedings of the conference on Design, automation and test in Europe
Pointer re-coding for creating definitive MPSoC models
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Sequential circuits for program analysis
Proceedings of the twenty-second IEEE/ACM international conference on Automated software engineering
Area optimisation for field-programmable gate arrays in SystemC hardware compilation
International Journal of Reconfigurable Computing - Selected Papers from SPL 2008: Programmable Logic and Applications
Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Finding the best compromise in compiling compound loops to Verilog
Journal of Systems Architecture: the EUROMICRO Journal
Computer-Aided Recoding to Create Structured and Analyzable System Models
ACM Transactions on Embedded Computing Systems (TECS)
Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Dynafuse: dynamic dependence analysis for FPGA pipeline fusion and locality optimizations
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the Conference on Design, Automation and Test in Europe
Throughput-oriented kernel porting onto FPGAs
Proceedings of the 50th Annual Design Automation Conference
Modeling and simulation in a formal design framework
Proceedings of the 6th Balkan Conference in Informatics
Efficient compilation of CUDA kernels for high-performance computing on FPGAs
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors
| Hi-index | 0.00 |
We present a high-level synthesis methodology that applies a coordinated set of coarse-grain and fine-grain parallelizing transformations. The transformations are applied both during a pre-synthesis phase and during scheduling, with the objective of optimizing the results of synthesis and reducing the impact of control flow constructs on the quality of results. We first apply a set of source level presynthesis transformations that include common sub-expression elimination (CSE), copy propagation, dead code elimination and loop-invariant code motion, along with more coarse-level code restructuring transformations such as loop unrolling. We then explore scheduling techniques that use a set of aggressive speculative code motions to maximally parallelize the design by re-ordering, speculating and sometimes even duplicating operations in the design. In particular, we present a new technique called "Dynamic CSE" that dynamically coordinates CSE and code motions such as speculation and conditional speculation during scheduling. We implemented our parallelizing high-level synthesis in the SPARK framework. This framework takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. Our results from computationally expensive portions of three moderately complex design targets, namely, MPEG-1, MPEG-2 and the GIMP image processing tool, validate the utility of our approach to the behavioral synthesis of designs with complex control flows.