Scheduling and binding algorithms for high-level synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
An efficient resource-constrained global scheduling technique for superscalar and VLIW processors
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Global scheduling with code-motions for high-level synthesis applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Module assignment for low power
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Behavioral network graph: unifying the domains of high-level and logic synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A reordering technique for efficient code motion
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A global resource-constrained parallelization technique
ICS '89 Proceedings of the 3rd international conference on Supercomputing
Speculation techniques for high level synthesis of control intensive designs
Proceedings of the 38th annual Design Automation Conference
High-Level VLSI Synthesis
A new symbolic technique for control-dependent scheduling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Incorporating performance and testability constraints during binding in high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Coordinated transformations for high-level synthesis of high performance microprocessor blocks
Proceedings of the 39th annual Design Automation Conference
Dynamic common sub-expression elimination during scheduling in high-level synthesis
Proceedings of the 15th international symposium on System Synthesis
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
SoC Synthesis with Automatic Hardware Software Interface Generation
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We introduce a code transformation technique, "conditional speculation", that speculates operations by duplicating them into preceding conditional blocks. This form of speculation belongs to a class of aggressive code motion techniques that enable movement of operations through and beyond conditionals and loops. We show that, when used during scheduling in a high-level synthesis system, this particular code motion has positive effect on latency and controller complexity, e.g., up to 35% reduction in longest path cycles and the number of states in the finite state machine (FSM) of the controller. However, it is not enough to determine complexity by the number of states in the control FSM. Indeed, the greater resource sharing opportunities afforded by speculation actually increase the total control cost (in terms of multiplexing and steering logic). This also adversely affects the clock period. We examine the effect of the various code motions on the total synthesis cost and propose techniques to reduce costs to make the transformations useful in real-life behavioral design descriptions. Using the MPEG-1 and ADPCM benchmarks, we show total reductions in schedule lengths of up to 50% while keeping control and area costs down.