Layout-driven high level synthesis for FPGA based architectures
Proceedings of the conference on Design, automation and test in Europe
Conditional speculation and its effects on performance and area for high-level snthesis
Proceedings of the 14th international symposium on Systems synthesis
High-Level Synthesis Methodology for On-Line Testability Optimization
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
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Module and register binding during high-level synthesis is one of the most important steps in generating an RTL design from a behavioral description. The binding phase determines the structure of the final design, and hence issues related to area, performance and testability of the RTL design have to be addressed in this step. In this paper, we present algorithms for module and register binding which generate RTL designs having high performance and/or high testability. The binding problem is decomposed into a sequence of subproblems, each of which is modeled as a minimum-cost network flow problem. The relative impact of the possible bindings is expressed in terms of the costs associated with the edges of the network. The model is simple and can be solved quickly to obtain a low cost flow solution. Putting together the solutions to the subproblems gives low cost bindings. We also propose cost functions that can be used with varying emphasis on delay and testing. The results demonstrate the effectiveness of our algorithm; the final designs produced by the algorithms require a smaller clock cycle or are easier to test as compared to designs generated without the performance or testability constraints