Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Incorporating testability considerations in high-level synthesis
Journal of Electronic Testing: Theory and Applications
Behavioral Testability Insertion for Datapath/Controller Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Improving Testability of Non-Scan Designs during BehavioralSynthesis
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Testability metrics for synthesis of self-testable designs and effective test plans
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Incorporating performance and testability constraints during binding in high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Introducing testability considerations as soon as possible in the design process results in more testable design with reduced area overhead. Very important improvements can be carried out before the scheduling step. An optimization, which takes effect at behavioral specifications and leads to produce an improved scheduling, is proposed by this study. This optimization is good for improving not only on-line testability but also for some other objectives in the obtained synthesis.