Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Bridge: a versatile behavioral synthesis system
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Condition graphs for high-quality behavioral synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Incorporating speculative execution in exact control-dependent scheduling
DAC '94 Proceedings of the 31st annual Design Automation Conference
Performance analysis and optimization of schedules for conditional and loop-intensive specifications
DAC '94 Proceedings of the 31st annual Design Automation Conference
Global scheduling for high-level synthesis applications
DAC '94 Proceedings of the 31st annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
Efficient encoding for exact symbolic automata-based scheduling
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Estimation of lower bounds in scheduling algorithms for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fine grain incremental rescheduling via architectural retiming
Proceedings of the 11th international symposium on System synthesis
Exploiting state equivalence on the fly while applying code motion and speculation
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A model for scheduling protocol-constrained components and environments
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A code-motion pruning technique for global scheduling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Behavioral-level partitioning for low power design in control-dominated application
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Layout-driven high level synthesis for FPGA based architectures
Proceedings of the conference on Design, automation and test in Europe
Speculation techniques for high level synthesis of control intensive designs
Proceedings of the 38th annual Design Automation Conference
Conditional speculation and its effects on performance and area for high-level snthesis
Proceedings of the 14th international symposium on Systems synthesis
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Coordinated transformations for high-level synthesis of high performance microprocessor blocks
Proceedings of the 39th annual Design Automation Conference
Clairvoyant: a synthesis system for production-based specification
Readings in hardware/software co-design
Efficient scheduling of conditional behaviors for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Arithmetic Operation Oriented Reconfigurable Chip: RHW
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Lower bound estimation of hardware resources for scheduling in high-level synthesis
Journal of Computer Science and Technology
A unified scheduling model for high-level synthesis and code generation
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A BDD-based frontend for retargetable compilers
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Combining MBP-speculative computation and loop pipelining in high-level synthesis
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Register Synthesis for Speculative Computation
EDTC '97 Proceedings of the 1997 European conference on Design and Test
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Constructive Method for Exploiting Code Motion
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A low-power scheduling tool for system on a chip designs
WSEAS Transactions on Circuits and Systems
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Register pressure aware scheduling for high level synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Clairvoyant: a synthesis system for production-based specification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal and heuristic algorithms for solving the binding problem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic memory access management for high-performance DSP applications using high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Modeling and simulation in a formal design framework
Proceedings of the 6th Balkan Conference in Informatics
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