Arithmetic Operation Oriented Reconfigurable Chip: RHW

Authors:
Tsukasa Yamauchi;Shogo Nakaya;Takeshi Inuo;Nobuki Kajihara
Affiliations:
-;-;-;-
Venue:
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Year:
2001

Citing 3
Cited 0

Global scheduling independent of control dependencies based on condition vectors

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
PipeRench: A Reconfigurable Architecture and Compiler

Computer
Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW

FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines

Quantified Score

Hi-index	0.00

Visualization

Abstract

We have developed an ALU based reconfigurable device called RHW (Reconfigurable HardWare) that is designed to work with the CPU to accelerate the computation-intensive part of the application by reconfiguring its data paths and ALUs optimized for the algorithm. It is also important to develop high performance operation unit library to utilize function cells of RHW efficiently. This paper describes the basic architecture of the RHW, high performance operation unit library and evaluation results.