Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A tree-based scheduling algorithm for control-dominated circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Area and performance optimizations in path-based scheduling
EURO-DAC '91 Proceedings of the conference on European design automation
Architectural retiming: pipelining latency-constrained circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
Fine grain incremental rescheduling via architectural retiming
Proceedings of the 11th international symposium on System synthesis
Exploiting state equivalence on the fly while applying code motion and speculation
DATE '99 Proceedings of the conference on Design, automation and test in Europe
High-level automatic pipelining for sequential circuits
Proceedings of the 14th international symposium on Systems synthesis
A processor-coprocessor architecture for high end video applications
Readings in hardware/software co-design
Register Synthesis for Speculative Computation
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Evaluator-executor transformation for efficient pipelining of loops with conditionals
ACM Transactions on Architecture and Code Optimization (TACO)
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Frequent control dependencies caused by IF- and loop-statements limit the parallelism usable in High-Level Synthesis. Loop pipelining is a powerful way to increase parallelism, but is often limited by these control dependencies. Multiple branch prediction (MBP-SC) applies loop pipelining and speculative computation to the most probable path and serves other paths during the restore phase (prediction error correction). In this paper we combine MBP-SC and loop pipelining and give a scheduling algorithm. Further MBP-SC improvement comes from parallel branch execution. The results show a considerable speedup compared to previous approaches.